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| PI2EQX3202B 3.2Gbps, 4 Differential Channel, Serial Re-Driver with Equalization, De-emphasis, and Squelch Features * * * * * * * * * * * * Supports data rates up to 3.2Gbps on each lane Optimized for SATA i/m operation Adjustable Transmiter De-Emphasis & Amplitude Adjustable Receiver Equalization Two Spread Spectrum Reference Clock Buffer Outputs Optimized for SATA applications Input signal level detection & output squelch on all channels 100-Ohm Differential CML I/O's Low Power (100mW per Channel) Standby Mode - Power Down State VDD Operating Range: 1.5V to 1.8V Packaging (Pb-free & Green): 84-ball LFBGA (NB84) Description Pericom Semiconductor's PI2EQX3202B is a low power, signal Re-Driver. The device provides programmable equalization, amplification, and de-emphasis by using 7 select bits, SEL[0:6], to optimize performance over a variety of physical mediums by reducing Inter-symbol Interference. PI2EQX3202B supports four 100-Ohm Differential CML data I/O's between the Protocol ASIC to a switch fabric, across a backplane, or to extend the signals across other distant data pathways on the user's platform. The integrated equalization circuitry provides flexibility with signal integrity of the signal before the Re-Driver. Whereas the integrated de-emphasis circuitry provides flexibility with signal integrity of the signal after the Re-Driver. A low-level input signal detection and output squelch function is provided for all four channels. Each channel operates fully independently. When a channel is enabled (EN_x=1) and operating, that channels input signal level (on xI+/-) determines whether the output is enabled. If the input level of the channel falls below the active threshold level (Vth-) then the outputs are driven to the common mode voltage. In addition to providing signal re-conditioning, Pericom's PI2EQX3202B also provides power management Stand-by mode operated by an Enable pin. Block Diagram Signal Detection LVCMOS Pin Description 1 A SD_C 2 SD_D 3 SEL0_A 4 SEL0_B 5 SEL4_A 6 SEL4_B 7 SEL6_A 8 SEL6_B 9 EN_A 10 EN_B SD_x CML CML xI+ Equalizer xISEL [0:2] EN_x Power Management SEL [2]_ x SEL [3]_ x Limiting Amp xOxO+ B VDD SD_B VDD SEL1_A SEL2_A SEL3_A SEL5_A VDD EN_C VDD C BO+ SD_A AI+ SEL1_B SEL2_B SEL3_B SEL5_B BI+ EN_D AO+ D BO- VDD AI- BI- GND AO- E GND VDD GND GND GND GND 84-Ball LFBGA F VDD GND VDD VDD GND VDD G DO+ SEL0_C CI+ DI+ SEL6_C CO+ -- Repeated 2 times -H DO- SEL0_D CI- VDD CKIN+ CKIN- GND DI- SEL6_D CO- CKINCKIN+ Buffer EN_ CLK OUTOUT+ J GND SEL1_C GND SEL2_C SEL2_D SEL3_D IREF GND SEL4_D GND IREF K EN_CLK SEL1_D SEL3_C SEL4_C OUT0+ OUT0- OUT1+ OUT1- SEL5_C SEL5_D 08-0103 1 PS8885G 04/30/08 PI2EQX3202B 3.2Gbps, 4 Differential Channel, Serial Re-Driver with Equalization, De-emphasis, and Squelch Pin Description Pin # B1, F1, D2, E2, B3, F3, H4, B8, F8, B10, F10 C3 D3 E1, J1, F2, E3, J3, H7, E8, J8, D9, E9, F9, E10, J10 C8 D8 G3 H3 G8 H8 A3, B4, B5 A4, C4, C5 G2, J2, J4 H2, K2, J5 B6, A5 C6, A6 K3, K4 J6, J9 B7, A7 C7, A8 K9, G9 K10, H9 C10 D10 C1 D1 G10 H10 G1 H1 A9, A10, B9, C9 Pin Name VDD AI+ AIGND BI+ BICI+ CIDI+ DISEL[0:2]_A SEL[0:2]_B SEL[0:2]_C SEL[0:2]_D SEL[3:4]_A SEL[3:4]_B SEL[3:4]_C SEL[3:4]_D SEL[5:6]_A SEL[5:6]_B SEL[5:6]_C SEL[5:6]_D AO+ AOBO+ BOCO+ CODO+ DOEN_ [A,B,C,D] I/O PWR I Description Supply Voltage, 1.5V to 1.8V 0.1V CML Input Channel A with internal 50 pull down PWR Supply Ground I I I I I I I I I I I I I I I O O CML Input Channel B with internal 50 pull down CML Input Channel C with internal 50 pull down CML Input Channel D with internal 50 pull down Selection pins for equalizer (see Amplifier Configuration Table) w/ 50k internal pull up Selection pins for amplifier (see Amplifier Configuration Table) w/ 50k internal pull up Selection pins for De-Emphasis (See De-Emphasis Configuration Table) w/ 50k internal pull up CML Output Channel A internal 50 pull up to VDD during normal operation and 2k when EN_A=0. Drives to output common mode voltage when input is O I 08-0103 2 PS8885G 04/30/08 PI2EQX3202B 3.2Gbps, 4 Differential Channel, Serial Re-Driver with Equalization, De-emphasis, and Squelch Pin # H6 H5 K5 K6 K7 K8 J7 K1 C2,B2,A1,A2 Pin Name CKINCKIN+ OUT0+, OUT0OUT1+, OUT1IREF EN_CLK SD_A, SD_B, SD_C, SD_D I/O I O Differential Reference Clock Input Description Differential Reference Clock Outputs O O I O External 475 resistor connection to set the differential output current Active HIGH LVCMOS signal input pin. When HIGH, it enables the OUTx+/OUTxoutputs. When LOW, it disables these outputs, with 50 to ground termination. Signal detect output. Provides a LVCMOS high output when a valid input signal is detected. When low, SD_X indicates that the input signal level is below the signal detect threshold level. Output Swing Control SEL3_[A:D] 0 0 1 1 SEL4_[A:D] 0 1 0 1 Swing 1x 0.8x 1.2x 1.4x Output De-emphasis Adjustment SEL5_[A:D] 0 0 1 1 SEL6_[A:D] 0 1 0 1 De-emphasis 0dB -2.5dB -3.5dB -4.5dB Equalizer Selection SEL0_[A:D] 0 0 0 0 1 1 1 1 SEL1_[A:D] 0 0 1 1 0 0 1 1 SEL2_[A:D] 0 1 0 1 0 1 0 1 Compliance Channel @ 1.6GHz No Equalization 0.5dB 0.5dB 1.5dB 1.0dB 2.5dB 1.0dB 3.5dB 1.0dB 4.5dB 1.0dB 5.5dB 1.0dB 6.5dB 1.0dB 08-0103 3 PS8885G 04/30/08 PI2EQX3202B 3.2Gbps, 4 Differential Channel, Serial Re-Driver with Equalization, De-emphasis, and Squelch Maximum Ratings (Above which useful life may be impaired. For user guidelines, not tested.) Storage Temperature........................................................ -65C to +150C Supply Voltage to Ground Potential ................................... -0.5V to +2.5V DC SIG Voltage ..........................................................-0.5V to VDD +0.5V Current Output ................................................................-25mA to +25mA Power Dissipation Continous ......................................................... 800mW Operating Temperature .............................................................. 0 to +70C Note: Stresses greater than those listed under MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. AC/DC Electrical Characteristics (VDD = 1.4V to 1.9V) Symbol Ps tPD Parameter Supply Power Latency Conditions EN = LVCMOS Low EN = LVCMOS High From input to output Min. Typ. Max. 0.1 0.6 Units W ns 2.0 CML Receiver Input Differential Input Peak-toVRX-DIFFP-P peak Voltage AC Peak Common Mode VRX-CM-ACP Input Voltage VTHSignal Detect Threshold DC Differential Input ZRX-DIFF-DC Impedance DC Input Impedance ZRX-DC Equalization JRS JRM Residual Jitter(1,2) Random Jitter(1,2) 0.200 150 EN_X = High 50 80 40 100 50 200 120 60 V mV mVp-p Total Jitter Deterministic jitter 1.5 0.3 0.2 Ulp-p psrms Notes 1. K28.7 pattern is applied differentially at point A as shown in Figure 1. 2. Total jitter does not include the signal source jitter. Total jitter (TJ) = (14.1 x RJ + DJ) where RJ is random RMS jitter and DJ is maximum deterministic jitter. Signal source is a K28.5 pattern (00 1111 1010 11 0000 0101) for the deterministic jitter test and K28.7 (0011111000) or equivalent for random jitter test. Residual jitter is that which remains after equalizing media-induced losses of the environment of Figure 1 or its equivalent. The deterministic jitter at point B must be from media-induced loss, and not from clock source modulation. Jitter is measured at 0V at point C of Figure 1. 08-0103 4 PS8885G 04/30/08 PI2EQX3202B 3.2Gbps, 4 Differential Channel, Serial Re-Driver with Equalization, De-emphasis, and Squelch FR4 Signal Source A B Pericom Re-Driver SmA Connector 30IN SmA Connector In Out C Figure 1. Test Condition Referenced in the Electrical Characteristic Table AC/DC Electrical Characteristics (VDD = 1.4V to 1.9V) Symbol Parameter Conditions Min. Typ. Max. Units CML Transmitter Output (100-Ohm differential) VDIFFP VTX-DIFFP-P VTX-C(4) tF, tR ZOUT ZTX-DIFF-DC CTX Output Voltage Swing | VTX-D+ - VTX-D- | Output Voltage Swing | VTX-D+ - VTX-D- | Common-Mode Voltage Transition Time Output Resistance DC Differential TX Impedance AC Coupling Capacitor | VTX-D+ - VTX-D- | / 2 20% to 80%(1) Single-ended 40 80 75 50 100 200 400(2) VDD 0.3 150 60 120 200 ps nF 600 1200(3) mVp-p mVp-pd LVCMOS Control Pins VIH VIL IIH IIL LVCMOS Outputs VOH VOL Output HIGH Voltage Output LOW Voltage IOH = -10mA IOL = 10mA VDD0.4 0.4 V V Input High Voltage Input Low Voltage Input High Current Input Low Current 0.65 x VDD VDD 0.35 x VDD 250 500 V A Note: 1. Using K28.7 (0011111000) pattern) 2. When 0.8x swing selected 3. When 1.4x swing selected 4. The parameter is determined by device characterization, and is not production tested 08-0103 5 PS8885G 04/30/08 PI2EQX3202B 3.2Gbps, 4 Differential Channel, Serial Re-Driver with Equalization, De-emphasis, and Squelch AC Switching Characteristics for Clock Buffer (VDD = 1.4 to 1.9V) (3) Symbol Trise / Tfall Trise / Tfall VHIGH VLOW VCROSS VCROSS TDC Parameters Rise and Fall Time (measured between 0.175V to 0.525V) Rise and Fall Time Variation Voltage High including overshoot Voltage Low including undershoot Absolute crossing point voltages Total Variation of Vcross over all edges Duty Cycle (input duty cycle = 50%) (2) (1) Min 125 Max. 525 75 Units ps Notes 1 1 1 660 -150 -200 200 45 900 550 250 55 % mV 1 1 1 2 Notes: 1. Measurement taken from Single Ended waveform. 2. Measurement taken from Differential waveform. 3. Test configuration is RS = 33.2, Rp = 49.9, and 2pF. Configuration Test Load Board Termination Rs 33 5% TLA CLKBUF Rs 33 5% TLB Rp 49.9 1% Rp 49.9 1% 2pF 5% Clock Clock# 2pF 5% 475 1% Figure 2. Configuration test load board termination Note: * TLA and TLB are 3" transmission lines. 08-0103 6 PS8885G 04/30/08 PI2EQX3202B 3.2Gbps, 4 Differential Channel, Serial Re-Driver with Equalization, De-emphasis, and Squelch 0.50 0.05 DATE: 08/19/05 DESCRIPTION: 84-Ball LFBGA PACKAGE CODE: NB-84 DOCUMENT CONTROL #: PD-2038 REVISION: C Ordering Information Ordering Number PI2EQX3202BNBE Package Code NB Package Description Pb-free & Green 84-Ball LFBGA Notes: * Thermal characteristics can be found on the company web site at www.pericom.com/packaging/ * E = Pb-free and Green * X suffix = Tape/Reel Pericom Semiconductor Corporation * 1-800-435-2336 * www.pericom.com 08-0103 7 PS8885G 04/30/08 |
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